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f85226 F85226F/fg lpc to isa bridge release date: july, 2007 revision: v0.25p
finte k feature integration technology inc. f85226 july, 2007 v0.25p i f8522 6 f85226 datasheet revision history version date page revision history 0.10p 2003/12/18 original vers ion (non register description) 0.20p 2003/12/23 added regist er and application circuit 0.21p 2003/12/29 3 removed pci 5v item of pin descriptions 5 revised the type descr iption of pin 92 from in ts to o 24 0.22p 2004/5/30 1 re vised features : fully isa bridge support except bus master (by conditions) 4 revised romcs#/rom_en pin?s description - revised register descriptions 0.23p 2004/8/17 37 update application circuit 0.24p 2005/04/15 34 added ?green package? ordering information 0.25p 2007/7/5 - company readdress please note that all data and specifications are subject to change without notice. all t he trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support applia nces, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for any damages resulting from such improper use or sales.
finte k feature integration technology inc. f85226 july, 2007 v0.25p ii f8522 6 table of contents 1. general de scripti on............................................................................................................ .. 1 2. featur es ....................................................................................................................... ........ 1 3. key specif icati ons ............................................................................................................. ... 1 4. block di agram .................................................................................................................. .... 2 5. pin config uration .............................................................................................................. .... 3 6. pin descr iptions............................................................................................................... ..... 3 6.1 power pin ...................................................................................................................... .4 6.2 power on str apping si gnal .............................................................................................. 4 6.3 lpc inte rface .................................................................................................................. 4 6.4 isa inte rface .................................................................................................................. .5 7. function de scripti on ........................................................................................................... 10 7.1 lpc interf ace: ............................................................................................................... 10 7.1.1 io/memory read and write c ycles ........................................................................... 12 7.1.2 dma read and writ e cycl es ..................................................................................... 12 7.1.3 booting memory read and write c ycles ................................................................... 12 7.2 serialized in terrupt ........................................................................................................ 13 7.3 lpc dm a...................................................................................................................... 14 8. registers de scripti on ......................................................................................................... 1 5 8.1 entry key. ..................................................................................................................... 15 8.2 configuration and control register ? index 03h ........................................................... 15 8.3 gpio1 function select r egister ? i ndex 04h ............................................................... 16 8.4 gpio2 function select r egister ? i ndex 05h ............................................................... 17 8.5 system clock register ? index 06h.............................................................................. 17 8.6 system power down regi ster ? i ndex 10h ................................................................... 18 8.7 gpio port define register ( low byte)? i ndex 11h ....................................................... 18 8.8 gpio port define register (high byte)? index 12h ...................................................... 19 8.9 address decoder regist er (i) ? i ndex 013h.................................................................. 19 8.10 address decoder register (ii) ? i ndex 014 h............................................................... 20 8.11 gpio input control regi ster ? in dex 15h.................................................................... 20 8.12 gpio output data regi ster ? in dex 16h..................................................................... 21 8.13 gpio1x input regist er ? index 17h ............................................................................ 21 8.14 gpio2 input control r egister ? i ndex 18h ................................................................. 22 8.15 gpio2 output data regi ster ? index 19h................................................................... 22 8.16 gpio2 input register ? index 1ah ............................................................................. 23 8.17 led & irqin control regi ster ? inde x 1bh ............................................................... 23
finte k feature integration technology inc. f85226 july, 2007 v0.25p iii f8522 6 8.18 master setting regist er ? index 1ch .......................................................................... 23 8.19 master setting regist er ? index 1dh .......................................................................... 24 8.20 refresh address register ( low byte) ? i ndex 1e h..................................................... 24 8.21 refresh address register ( high byte) ? in dex 1fh .................................................... 24 8.22 address1 decode mask regi ster ? index 20h............................................................ 24 8.23 address1 decode register (low byte) ? index 21h ................................................... 24 8.24 address1 decode register (high byte) ? index 22h .................................................. 25 8.25 address2 decode mask regi ster ? index 23h............................................................ 25 8.26 address2 decode register (low byte) ? index 24h ................................................... 25 8.27 address2 decode register (high byte) ? index 25h .................................................. 25 8.28 rom1 decoder mask low byte register ? in dex 0x28.............................................. 26 8.29 rom decoder mask (high byte) register ? i ndex 0x 29............................................. 26 8.30 rom decoder address (low byte ) register ? index 0x 2a......................................... 26 8.31 rom decoder address (high byte ) register ? index 0x 2b ........................................ 26 8.32 rom2 decoder mask low byte register ? in dex 0x2c ............................................. 27 8.33 rom2 decoder mask (high byte ) register ? index 0x2d .......................................... 27 8.34 rom2 decoder address (low by te) register ? index 0x2e....................................... 27 8.35 rom2 decoder address (high by te) register ? index 0x 2f ...................................... 27 8.36 addr3 decoder mask high byte register ? i ndex 0x30 ........................................... 28 8.37 addr3 decoder address low byte register ? index 0x31........................................ 28 8.38 addr3 decoder address high byte register ? index 0x 32 ....................................... 28 8.39 addr4 decoder mask high byte register ? i ndex 0x33 ........................................... 28 8.40 addr4 decoder address low byte register ? index 0x34........................................ 29 8.41 addr4 decoder address high byte register ? index 0x 35 ....................................... 29 8.42 kbc decoder mask regist er ? index 0x36 ................................................................ 29 8.43 kbc decoder address low byte register ? index 0x37 ............................................ 30 8.44 kbc decoder address high byte register ? index 0x38............................................ 30 8.45 mc decoder mask regist er ? index 0x39 .................................................................. 30 8.46 mc decoder address low byte register ? index 0x3a.............................................. 30 8.47 mc decoder address high byte register ? index 0x3b ............................................. 31 8.48 rtc decoder mask regist er ? index 0x3c ................................................................ 31 8.49 rtc decoder address low byte register ? index 0x3d ............................................ 31 8.50 rtc decoder address high byte register ? index 0x3e ........................................... 31 8.51 ioh decoder mask regist er ? index 0x3f ................................................................. 32 8.52 ioh decoder address low byte register ? index 0x40 ............................................. 32 8.53 ioh decoder address high byte register ? index 0x41............................................. 32 8.54 edge detector status r egister ? i ndex 0x50 .............................................................. 32
finte k feature integration technology inc. f85226 july, 2007 v0.25p iv f8522 6 8.55 irq wakeup register (i) ? index 0x51 ....................................................................... 33 8.56 irq wakeup register (i i) ? index 0x52 ...................................................................... 33 8.57 chipid (1) register ? index 5ah................................................................................ 33 8.58 chipid (2) register ? index 5bh................................................................................ 33 8.59 version register ? index 5ch ................................................................................. 34 8.60 vendor id (1) regist er ? index 5dh........................................................................ 34 8.61 vendor id (2) regist er ? index 5eh ........................................................................ 34 9. ordering info rmation ......................................................................................................... 34 10. electrical char acterist ic .................................................................................................... 34 9.1 absolute maxi mum rati ngs .......................................................................................... 34 9.2 dc characteri stics........................................................................................................ 35 11. package specif icatio n ...................................................................................................... 36 12. applicatio n circu it ............................................................................................................ 37
finte k feature integration technology inc. f85226 july, 2007 v0.25p 1 f8522 6 1. general description the f85226 is a lpc to isa bridge ic for new generation chipset which is no support for isa bus and slots. however the demand of isa dev ices still exists. therefore lpc to isa bridge ic is necessary to be used for new chipset system. the f85226 is the best selection even though there is the pci to isa bridge for supporting isa device, because the issue of package size is critical for layout requirement. follows the point at these issues, the f85226 is optimal soluti on for the non-isa chipset, the package of f85226 will be the best chosen for economic solution and sa ve the layout size of motherboard. the f85226 absolutely meets lpc spec. 1.1 and sup ports fully isa interface. provides multi-isa compatible slots without buffering and supports isa paralle l irq transfer to serial irq by irq serialier. the f85226 also provides programmable general purpose i/o pins for user. it is completely lpc to isa bridge specialized chip. 2. features meets lpc spec. 1.1 supports ldrq#(lpc dma), serirq(serial irq) fully isa bridge support exc ept bus master(by conditions) supports 8/16bit i/o and memory r/w all software transparent all isa signals can be isolate isa parallel irq transfer to serial irq by irq serialier supports multi-slots without buffering supports the pci clock to divide by 3 or 4 for isa bus supports to generate two 14.318mhz buffer out from one 14.318mhz in 4 sets of address decoder supported supports programmable general purpose i/o pins powered by 3vcc (signal 5v tolerance) 128pin pqfp package 3. key specifications supply voltage 3.0v to 3.6v operating supply current 4ma typ.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 2 f8522 6 lpc interface signal power down control power supply clk gen./buf . isa interface ??????? 14.318m 14mout1 14mout2 3.3v pwrdn# pcirst# lfram# ldrq# pciclk serirq lad [3:0] dack [0:3,5:7] drq [0:3,5:7] irq [3:7,9:12,14,15] sa [19:0] sd [15:0] aen bale iochrdy 4. block diagram
finte k feature integration technology inc. f85226 july, 2007 v0.25p 3 f8522 6 5. pin configuration 6. pin descriptions i/o 24ts - ttl level bi-directional pin and schmitt trigger with 24 ma source-sink capability. i/od 24ts_u100k - ttl level input pin and schmitt trigger, open-drain output with 24 ma sink capability, internal pull-up 100k ? connected with 3.3v to protect electric leakage. i/o 24ts_u100k - ttl level input pin and schmitt trigger, output pin with 24 ma sink capability, internal pull-up 100k ? connected with 3.3v to protect electric leakage. o 24_u100k - output pin with 24 ma source -sink capability, internal pull-up 100k ? connected with 3.3v to protect electric leakage. o 24 - output pin with 24 ma source-sink capability. o 20 - output pin with 20 ma source-sink capability. 3.3v 100k f85226
finte k feature integration technology inc. f85226 july, 2007 v0.25p 4 f8522 6 in t - ttl level input pin. in ts - ttl level input pin and schmitt trigger. p - power. 6.1 power pin pin no. pin name type description 5, 20, 25, 45, 55, 70, 85, 105, 120 vdd3v p st andard power supply voltage input with 3.3v. 15, 30, 50, 60, 80, 95, 110, 125 gnd p ground. 6.2 power on strapping signal pin no pin name type pwr description 36 80pcs#/kben# i/od 24ts_u100k (5v-tolerance) vdd3v power-on strapping with external pulled-down resistor 10k will enable k/b and mouse functions. when it is set, pin 38, 39 and 40 will execute irq1, kbcs# and mccs# signals. 37 romcs#/rom_en i/o 24ts (5v-tolerance) vdd3v power-on strapping without internal resister, need external pulled-up resistor to enable cr03h (bios_rom_en bit) if there is a boot-rom (bios). else if wit hout boot-rom, please use external pulled-down 10k resister to disable this bios_rom_en. 126 dack7#/rtcen# i/o 24ts_u100k (5v-tolerance) vdd3v power-on strapping with external pulled-down 10k resistor will enable rtc functions. when it is set, pin 64 and 65 will do irq8 and rtccs# signals. 128 dack6#/hefras i/o 24ts_u100k (5v-tolerance) vdd3v set this function will change the port that is used to access configuration registers. default setting is 4eh, but by power-on strapping with a external pulled-down 10k resister change to 2eh. 2 dack5#/en_gp2x i/o 24ts_u100k (5v-tolerance) vdd3v power-on strapping with external pulled-down 10k resistor. then it will disable la [19:17] function an d pin108~pin111, pin29 use as gpio2x function. 6.3 lpc interface pin no. pin name type pwr description 16-19 lad[3:0] i/o 24ts vdd3v multiplexed command, address bi-dir ectional data and cycle status. through the lpc bus between a host and a peripheral. 13 lframe# in ts vdd3v low pulse indicates start of a new cycle or termination of broken cycle. 21 pciclk in t vdd3v pci clock used for the lpc bus. same 33mhz clock as pci clock on the host. same clock phase with typical pci skew.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 5 f8522 6 14 pcirst# in ts vdd3v pci system reset used for the lpc bus. the reset signal line can be connected to pcirst# signal on the host. 23 serirq i/o 24ts vdd3v serial irq input/output. 22 ldrq# o 24 vdd3v encoded dma request signal. 24 pwrdn# in ts vdd3v power down. the signal is active low according to cr 44 bit 7and wake-up enable by hardware setting. there are eight different power-down states (power down mode 3). 6.4 isa interface pin no. pin name type pwr description 58-56 sa[19:17] i/o 24ts_u100k (5v-tolerance) vdd3v system address bus. these are the upper addresses that define the isa?s byte address space (up to 1 m byte). the sa [19:17] are at tri-states during pcirst#. 54-51 49-46 44-41 35-31 sa[16:0] i/o 24ts_u100k (5v-tolerance) vdd3v system address bus. these define the isa?s byte address space (up to 128k byte). the sd [16:0] are at tri-states during pcirst#. 122-121 119-114 75-71 69-67 sd[15:0] i/o 24ts_u100k (5v-tolerance) vdd3v system data bus. these provide 16-bit data for devices to reside on the isa bus. the sd [15:0] ar e at tri-states during pcirst#. 59 aen o 24 (5v-tolerance) vdd3v address enable. aen is asserted during dma cycles, driven high during f85226 initiated refresh cycles, driven low upon pcirst#. 86 ior# i/o 24ts_u100k (5v-tolerance) vdd3v i/o read. ior# is asserted to request an isa i/o slave to drive data onto the data bus. 84 iow# i/o 24ts_u100k (5v-tolerance) vdd3v i/o write. iow# is asserted to request an isa i/o slave to accept data from the data bus. 61 iochrdy i/o 24ts (5v-tolerance) vdd3v i/o channel ready. iochdry asse rted indicates that an isa slave requires additional wait st ates. when the f85226 is an isa slave, iochrdy is an output indicati ng additional wait states are required. 92 sysclk o 24 vdd3v isa system clock. sysclk offers the reference clock to the isa bus. the frequency is generated from dividing pciclk by 3 or 4 (select by cr06 bit7). 77 rstdrv o 24 vdd3v reset drive. rstdrv asserted indicates to reset devices that reside on the isa bus while the pcirst# has been asserted.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 6 f8522 6 11 iocs16# i/o 24ts (5v-tolerance) vdd3v 16-bit i/o chip select. iocs16# is asserted by 16-bit isa i/o devices to indicate that they support 16-bit i/o bus cycles. 12 memcs16# i/o 24ts (5v-tolerance) vdd3v memory chip select 16. memcs1 6# is asserted by 16-bit isa memory devices to indicate that the memory slave supports 16-bit accesses. 76 iochck# in ts (5v-tolerance) vdd3v i/o channel check. asserted by an isa device indicating an error condition. 81 ows# in ts (5v-tolerance) vdd3v zero wait states. an isa slave asserts zerows# after its address and command signals have been decoded to indicate that the current cycle can be execut ed as an isa zero wait state cycle. zerows# has no effect during 16-bit i/o cycles. 103-104 106-107 la[23:20] i/o 24ts_u100k (5v-tolerance) vdd3v unlatched address. the la [23:20] address lines are bi-directional. these address lines allow accesses to physical memory on the isa bus up to 16 mbytes. la [23:20] are outputs when the f85226 owns the isa bus. la[19:17] unlatched address. the la [19:17] address lines are bi-directional. these address lines allow accesses to physical memory on the isa bus up to 16 mbytes. la [19:17] are outputs when the f85226 owns the isa bus. 108-109 111 gp23, gp22, gp21 i/o 24ts_u100k (5v-tolerance) vdd3v general purpose i/o pin. 82 smemw# o 24 (5v-tolerance) vdd3v standard (system) memory write. smemw# is asserted for memory write accesses below 1mb. 83 smemr# o 24 (5v-tolerance) vdd3v standard (system) memory read. smemr# is asserted for memory read accesses below 1 mb. 91 refresh# o 24_u100k (5v-tolerance) vdd3v refresh cycle indicator. refresh# asserted indicates that a refresh cycle is in progress, or isa master requests f85226 to generate a refresh cy cle. the signal is at tri-stated upon pcirst#. 101 bale i/o 24ts_u100k (5v-tolerance) vdd3v bus address latch enable. bale asserted indicates when the address (sa[19:0], la[23:17]) and sbhe# are valid. the la [23:17] address lines are latched on the trailing edge of bale. bale is driven by low upon pcirst#. 102 sbhe# i/o 24ts_u100k (5v-tolerance) vdd3v system byte high enable. sbhe# asserted indicates that sd[15:8] will be used to transfer a byte. sbhe# is at an unknown state upon pcirst#. 112 memr# i/o 24ts_u100k (5v-tolerance) vdd3v memory read. memr# asserted indicates the current isa bus cycle is a memory read. 113 memw# i/o 24ts_u100k (5v-tolerance) vdd3v memory write. memw# asserted indicates the current isa bus cycle is a memory write.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 7 f8522 6 123 master# in ts (5v-tolerance) vdd3v the master# input asserted indicates an isa bus master is driving the isa bus. this signal is executed with dreq line by an isa master to gain control of the isa bus. 98 irq3 in ts (5v-tolerance) vdd3v parallel interrupt requested input 3. 97 irq4 in ts (5v-tolerance) vdd3v parallel interrupt requested input 4. 96 irq5 in ts (5v-tolerance) vdd3v parallel interrupt requested input 5. 94 irq6 in ts (5v-tolerance) vdd3v parallel interrupt requested input 6. 93 irq7 in ts (5v-tolerance) vdd3v parallel interrupt requested input 7. 78 irq9 in ts (5v-tolerance) vdd3v parallel interrupt requested input 9. 10 irq10 in ts (5v-tolerance) vdd3v parallel interrupt requested input 10. 9 irq11 in ts (5v-tolerance) vdd3v parallel interrupt requested input 11. 8 irq12 in ts (5v-tolerance) vdd3v parallel interrupt requested input 12. 6 irq14 in ts (5v-tolerance) vdd3v parallel interrupt requested input 14. 7 irq15 in ts (5v-tolerance) vdd3v parallel interrupt requested input 15. 3 drq0 in ts (5v-tolerance) vdd3v dma request input 0. the dreq a sserted indicates that either a slave dma device is requesting dma services or an isa bus master is requesting to use the isa bus. 90 drq1 in ts (5v-tolerance) vdd3v dma request input 1. 79 drq2 in ts (5v-tolerance) vdd3v dma request input 2. 88 drq3 in ts (5v-tolerance) vdd3v dma request input 3. 1 drq5 in ts (5v-tolerance) vdd3v dma request input 5.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 8 f8522 6 127 drq6 in ts (5v-tolerance) vdd3v dma request input 6. 124 drq7 in ts (5v-tolerance) vdd3v dma request input 7. 4 dack0# o 24 (5v-tolerance) vdd3v dma acknowledge channel 0. the dack# outputs asserted indicates that either a dma chan nel or an isa bus master has been granted the isa bus. 89 dack1# o 24 (5v-tolerance) vdd3v dma acknowledge channel 1. 99 dack2# o 24 (5v-tolerance) vdd3v dma acknowledge channel 2. 87 dack3# o 24 (5v-tolerance) vdd3v dma acknowledge channel 3. dack5# dma acknowledge channel 5. 2 en_gp2x i/o 24ts_u100k (5v-tolerance) vdd3v during power-on strapping with external pulled-down 10k resistor. then it will disable la [19:17] function and pin108~pin111, pin29 use as gpio2x function. dack6# dma acknowledge channel 6. 128 herfra i/o 24ts_u100k (5v-tolerance) vdd3v during power-on reset, this pin is pulled-up internally(select 4eh) ,and is defined as hefr as which provides the power-on value for cr3 bit4 .a 10k ohm is recommended if intends to pull down .(select 2eh) dack7# dma acknowledge channel 7. 126 rtcen# i/o 24ts_u100k (5v-tolerance) vdd3v rtc function enable. the pin applies a pull-down resistor (4.7k ohm) to enable rtc functions (rtccs#, and irq8) 100 tc o 24 (5v-tolerance) vdd3v terminal count. tc signals the final data transfer of a dma transfer. 80pcs# 80h port chip select.(default) only decode io address port 80h and must apply with iow#. 36 kben# i/od 24ts_u100k (5v-tolerance) vdd3v k/b functions enable. during power-on reset this pin is weak pulled-up internally. the pin applied a pull-down resistor (10k ohm) to enable k/b functions . (irq1,kbcs#,and mccs#) 37 romcs# i/o 24ts (5v-tolerance) vdd3v romcs#, this pin enable positive decoder of bios address range.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 9 f8522 6 rom_en power-on strapping with internal pulled-up resistor will enable cr03h (bios_rom_en, bios_wr_en bit). if there is a boot-rom (bios), else if without boot-rom, please use external pulled-down 10k resister to disable this rom_en and wr_en. gpio0 general purpose i/o pin 0. 38 irq1 i/o 24ts (5v-tolerance) vdd3v parallel interrupt requested input 1. this pin is used for specific k/b functions. gpio1 general purpose i/o pin 1. 39 kbcs# i/o 24t (5v-tolerance) vdd3v decode address 60h and 64h to generate chip selected signal. enable by kben# power-on setting. gpio2 general purpose i/o pin 2. 40 mccs# i/o 24ts (5v-tolerance) vdd3v decode address 62h and 66h to generate chip selected signal. enable by kben# power-on setting. gpio3 general purpose i/o pin 3. 62 irqin i/o 24ts (5v-tolerance) vdd3v it is programmable to transfer paral lel irq input to serial irq, enable by kben# power-on setting. gpio4 general purpose i/o pin 4. 63 pled i/o 24ts (5v-tolerance) vdd3v power led output, the signal is at low state after system reset. gpio5 general purpose i/o pin 5. 64 irq8 i/o 24ts (5v-tolerance) vdd3v parallel interrupt requested input 8. this interrupt request is used for specific rtc functions. enable by rtcen# power-on setting. gpio6 general purpose i/o pin 6. 65 rtccs# i/o 24ts (5v-tolerance) vdd3v decode address 70h and 71h to generate chip selected signal. enable by rtcen# power-on setting. gpio7 general purpose i/o pin 7. 66 iohcs# i/o 24ts (5v-tolerance) vdd3v decode sa [15-11] all are at ?0? state initially and setting by cr04 bit 6. 26 14.318m in ts (5v-tolerance) vdd3v 14.318 mhz clock input. 27 14mout 1 o 20 vdd3v 14.318 mhz buffer output 1. 28 14mout 2 o 20 vdd3v 14.318 mhz buffer output 2. gp20 general purpose i/o pin. 29 pled i/o 24ts (5v-tolerance) vdd3v power led output, the signal is at low state after system reset.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 10 f8522 6 7. function description 7.1 lpc interface: the f85226 implemented full functions that described in the lpc i/f 1.1 specification and transfers all subtractive cycles from lpc bus to isa interface for more isa compatibility. the f85226 built in 16-bit io/ memory enhances transaction. peripheral or master devices can assert cycles that are not defined in positive decode ranges of lpc interf ace. all lpc bus signals use pci electrical characteristics. the following cycle types are supported by f85226. z io read write (8 / 16 bit) z memory read write (8 / 16 bit) z dma read write (8/ 16 / 32 bit) z firmware memory read write (only support size 8 or 16 bit). ecycles : s: start cycle c: command type cycle cycle types encoding remark io read s: 0x0h; c: 0x0h size: 8 bit and 16 bit in enhanced mode, for lpc peripheral. io write s: 0x0h; c: 0x2h size: 8 bit and 16 bit in enhanced mode, for lpc peripheral. memory read s: 0x0h; c: 0x4h size: 8 bit and 16 bit in enhanced mode, for lpc peripheral and host. memory write s: 0x0h; c: 0x6h size: 8 bit and 16 bit in enhanced mode, for lpc peripheral and host. dma read s: 0x0h; c: 0x8h size: 8, 16 and 32 bit, for lpc peripheral. dma write s: 0x0h; c: 0xah size: 8, 16 and 32 bit, for lpc peripheral. booting memory read s: 0xdh; size: 8, 16, 32 and 1024 bit, for lpc peripheral. booting memory write s: 0xeh; size: 8, 16, and 32 bit, for lpc peripheral. start: the cycle indicates the beginning or abort of a transac tion. when lframe# is asserted low and monitors lad[3:0] that determine frame type to enter a valid start. cycle type and direction: lpc host will issue the transaction cycle and dire ction by lad[3:1] and lad0 is always ignored.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 11 f8522 6 size: lpc host on dma or bus master on memory transacti on issue data size that will be transferred by lad[1:0] and lad[3:2] must be driven 0x00b. turn-around: lpc host or peripheral will issue two clock wide cycles after turning control over to peripheral or turning back from peripheral to host. lad[3:0] should be driven to high level on first cycle and release to tri-state on next one. address: while doing io transaction, this duration is four clock wide that indicates 16-bit address, on memory cycles there are eight clocks that indicates 32-bit address will be asserted by lpc host or master. the duration is not asserted on dma transaction. channel and terminal count: only on dma transferring, lad[2:0] signals indicate granted channel in one clock cycle. lad[3] indicates terminal count down. data: each frame can carry one byte (8 bit), firs t nibble is data[7;4] and next is data[3:0]. sync: lpc host or peripheral can add wait state, response error and ready to accept a frame by lad[3:0]. 0x0h: ready 0x5h: short wait, maximum number of sync is 8 clocks. 0x6h: long wait, no maximum number. 0x9h: ready more on dma transaction. 0xah: error, it relates to iochk# on isa interface. others: reserved. sta : .. start cycle ct : .. cycle type and direction h_tar: . host turn-around p_tar: peripheral turn-around ct addr[15:0]/ [31:0] h_tar sync sync sync data[7:0] data[7:0] lclk lframe# lad[3:0] p_tar sta figure: read cycles
finte k feature integration technology inc. f85226 july, 2007 v0.25p 12 f8522 6 ct addr[15:0]/ [31:0] h_tar sync sync sync p_tar data[7:0] data[7:0] lcl k lframe# lad[3:0] sta figure: write cycles 7.1.1 io/memory read and write cycles when lpc interface bridge issues io cycles t hat meet subtractive decode, f85226 will assert corresponded ior#, iow# , memr# ,smemr# , memw# and smemw# then respond by inserting wait cycles (long wait sync). after finishing isa transaction and there isn?t any valid isa wait state inserted, it responds ready-state and terminates the cycles. if the host iss ues 16 bit transfer, f85226 will active enhance 16-bit transferring function automatically. 7.1.2 dma read and write cycles the read transactions transfer data from main memory to peripheral and write cycles transfer data from peripheral to main memory. dma requests form isa interface are delivered by ldrq# to dma controller (like 8237) and the acknowledge responds fr om lad [3:0] encoding message. terminal count is depended on the counter programmed in dma controller, w hen reach the counter threshold, tc is related to lad3 and asserted when dma controlle r plan to terminal dma transaction. 7.1.3 booting memory read and write cycles the isa interface of f85226 can communicate to isa rom (system bios) with romcs#, memer# and memw#, bios booting cycles of pc system may assert through different cycle type ( like memory read and firmware memory read) , f85226 can perfor m a positive decoder on specified memory range included legacy bios , extended legacy bios and user defined high memory address.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 13 f8522 6 legacy bios extended bios 0x000fffffh 0x000f0000h 0x000e0000h 0xffffffffh 0xffe00000h romcs# 0x00000000h figure: chip select of bios memory 7.2 serialized interrupt serial interrupt is a single bus that transmits paralle l legacy interrupts and encodes suitable packet at corresponded moment. the signal refers to lclk and it operates on an open-drain bus (multi-drop bus) that is shared with other devices. f85226 supports two operation types included continuous and quiet mode. eventually, it fully meets ser irq specification version 6.0. r: recovery phase, serirq signal is driven to high level t: turn-around phase, devices tri-state serirq, s: sampling phase, serirq signal is sink to low level lclk serirq start rt s rt s rt stop irqx to identify parallel irq type on serirq, following the table list supported source. one serirq field contains three states included recovery, turn-around and sample.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 14 f8522 6 serirq field parallel irq number of clocks after start finished (rising edge) 1 reserved 2 2 reserved 5 3 reserved 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 reserved 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 reserved 41 15 irq14 44 16 irq15 47 17 iochk# 50 21:18 reserved 53, 56, 59 , 62 table: serirq map 7.3 lpc dma lpc dma supports signal, demand, verify and increment operations. the dma channels are compatible with isa interface. all channels can be encod ed to ldrq# in serial format even channel 4 that requests a bus master to lpc host. channels 0-3 are for 8-bit transaction and channel 5-7 are for 16-bit transaction. f85226 also supports 32-bit dma if lpc host issues. ldrq# also refers to lclk and samples in negative edge by lpc host. act field indicates the dma aborts or not. lclk ldrq# start msb lsb act start figure: lclk and ldrq#
finte k feature integration technology inc. f85226 july, 2007 v0.25p 15 f8522 6 8. registers description 8.1 entry key: write 26h to the location 4eh ( default ) twice will enable the following configuration registers. change the location to 2eh by power-on strappi ng with an external pulled-down resister on pin 128. 8.2 configuration and cont rol register ? index 03h power-on default [7:0] =00_100_0_s_0b (s: m ean default value effect by strapping) bit name r/w pwr description 7-6 rom_sel_type r/w vdd3v 00: romcs# decoder addr ess 0xf_xxxx, and 0xe_xxxx if bios_0e_en set to 1 (reg03h bit0). 01: romcs# decoder address by define address 1 (reg2ah, 2bh) and define address 2 (reg 2eh, 2fh). 10: romcs# decoder address 0xf_xxxx, and 0xe_xxxx if bios_0e_en set to 1 (reg03h bit0) or romcs# decoder address by define address 1 (reg2ah, 2bh) and define address 2 (reg 2eh, 2fh). 11: romcs# decoder address 0xf_xxxx, and 0xe_xxxx if bios_0e_en set to 1 (reg03h bit0) or romcs# decoder address by define address 1 (reg2ah, 2bh) and define address 2 (reg 2eh, 2fh). 4-2 bios_rom_size r/w vdd3v 000: romcs# decodes range 1m. 001: romcs# decodes range 2m. 010: romcs# decodes range 4m. 011: romcs# decodes range 8m. 100: romcs# decodes range 16m. 101: romcs# decodes range 32m. 110: romcs# decodes range 64m. 111: romcs# decodes range 1m. 2 bios_0e_en r/w vdd3v enable romc s# to decode the address 0xe_xxxx. 1 bios_rom_en r/w vdd3v enable romcs# to decode address. 0 bios_wr_en r/w vdd3v when bios_rom_en is enabled, sets this bit to protect bios write.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 16 f8522 6 8.3 gpio1 function select register ? index 04h power-on default [7:0] =0ss0_ssssb bit name r/w pwr description 7 gp17_mode r/w vdd3v set this bit to 0, the pin gp17/iohcs# will be used as gp17 function. set to 1, the pin gp17/iohcs# used as iohcs# function and decode range can program by (reg 0x3f~0x41). 6 gp16_mode r/w vdd3v set this bit to 0, the pin gp16/rtccs# will be used as gp16 function. set to 1, the pin gp16/rtccs# used as rtccs# function and decode range can program by (reg 0x3c~0x3e). the default value is strapping by rtcen. 5 gp15_mode r/w vdd3v set this bit to 0, the pin gp15/irq8 will be used as gp15 function or gpcs#. set to 1, the pin gp15/irq8 used as irq8. the default value is strapping by rtcen. 4 gp14_mode r/w vdd3v set this bit to 0, the pin gp14/pled1 will be used as gp14 function. set to 1, the pin gp12/pled1 used as pled1. 3 gp13_mode r/w vdd3v set this bit to 0, the pin gp13/irqin will be used as gp13 function. set to 1, the pin gp13/irqin used as irqin function. the default value is strapping by kben 2 gp12_mode r/w vdd3v set this bit to 0, the pin gp12/mccs# will be used as gp12 function. set to 1, the pin gp12/mccs# used as mccs# function and decode range can program by (reg 0x39~0x3b). the default va lue is strapping by kben 1 gp11_mode r/w vdd3v set this bit to 0, the pin gp11/kbcs# will be used as gp11 function. set to 1, the pin gp11/kbcs# used as kbcs# function and decode range can program by (reg 0x36~0x38). the default value is strapping by kben 0 gp10_mode ro vdd3v set this bit to 0, the pin gp10/irq1 will be used as gp10 function or gpcs#. set to 1, the pin gp10/irq1 used as irq1. the default value is strapping by kben. 0xffff_ffff 0x000f_ffff 0xffff_0000 0x000e_0000 0xffff_ffff 0x000f_ffff 0xffff_0000 0x000f_0000 bios_oe_en = 1 rom_sel_type =0 bios_oe_en = 0 rom_sel_type =0 0xffff_ffff 0x000f_ffff 0xffff_0000 0x000f_f000 bios_oe_en = 1, rom_sel_type =1 reg 2bh = 0xff, reg 2ah = 0xff reg 29h = 0x00, reg 28h = 0xff reg 2fh = 0xcf, reg 2eh = 0xff reg 2dh = 0x00, reg 2ch = 0xff 0x000c_ffff 0x000c_f000 0xffff_ffff 0x000f_ffff 0xffff_0000 bios_oe_en = 1, rom_sel_type =2 reg 2bh = 0xff, reg 2ah = 0xff reg 29h = 0x00, reg 28h = 0xff reg 2fh = 0xcf, reg 2eh = 0xff reg 2dh = 0x00, reg 2ch = 0xff 0x000c_ffff 0x000c_f000 0x000e_0000 0xffff_ffff 0x000f_efff 0xffff_0000 bios_oe_en = 1, rom_sel_type =3 reg 2bh = 0xff, reg 2ah = 0xff reg 29h = 0x00, reg 28h = 0xff reg 2fh = 0xcf, reg 2eh = 0xff reg 2dh = 0x00, reg 2ch = 0xff 0x000c_ffff 0x000c_f000 0x000e_0000 bios_rom_siez = 00
finte k feature integration technology inc. f85226 july, 2007 v0.25p 17 f8522 6 8.4 gpio2 function select register ? index 05h power-on default [7:0] =0000_sss0b bit name r/w pwr description 7-5 reserved ro vdd3v 3 gp23_mode r/w vdd3v set this bit to 0, the pin sa19/gp23 will be used as gp23 function or gpcs#. set to 1, the pin sa19/gp23 used as sa19. the def ault value is strapping by dack5#. 2 gp22_mode r/w vdd3v set this bit to 0, the pin sa18/gp22 will be used as gp22 function or gpcs#. set to 1, the pin sa18/gp22 use as sa18. the default value is strapping by dack5#. 1 gp21_mode r/w vdd3v set this bit to 0, the pin sa17/gp21 will be used as gp21 function or gpcs#. set to 1, the pin sa17/gp21 used as sa17. the def ault value is strapping by dack5#. 0 gp20_mode r/w vdd3v set this bit to 0, the pin gp20/pled0 will be used as gp20 function or gpcs#. set to 1, this pin will be used as pled0 output. (when use in led mode, gp20 output control ?cr18? must select to output mode, and user need to take care that decoder se lect ?cr13,14? can?t select to pin gp20). 8.5 system clock re gister ? index 06h power-on default [7:0] =0000_0000b bit name r/w pwr description 7 sysclk_sel r/w vdd3v set to 1, isa system clock period will be 3 pci clock. set to 0, system clock period will be 4 pci clock. 6 en_recover8 r/w vdd3v set to 1, enable bit [5:3] se tting. set to 0, disable bit [5:3] setting and uses 3.5 sysclks for 8 bits i/o recovery time. 5-3 recover_time8 r/w vdd3v when bit 6 was set to 1, these 3 bits field define the additional number of sysclks added to standard 3.5 sysclks recovery time for 8 bits i/o. = 000 --- 0 sysclk = 001 --- 1 sysclk = 010 --- 2 sysclks = 011 --- 3 sysclks = 100 --- 4 sysclks = 101 --- 5 sysclks = 110 --- 6 sysclks = 111 --- 7 sysclks 2 en_recover16 r/w vdd3v set to 1, enable bit [1:0] se tting. set to 0, disable bit [1:0] setting and uses 3.5 sysclks for 16 bits i/o recovery time. 1-0 recover_time16 r/w vdd3v .when bit 2 was set to 1, these 3 bits field define the additional number of sysclks added to standard 3.5 sysclks recovery time for 16 bits i/o. = 01 --- 1 sysclk = 10 --- 2 sysclk s
finte k feature integration technology inc. f85226 july, 2007 v0.25p 18 f8522 6 = 11 --- 3 sysclk s = 00 --- 4 sysclk s 8.6 system power down register ? index 10h power-on default [7:0] =0011_0000b bit name r/w pwr description 7 reserved r/w vdd3v 6 soft_down r/w vdd3v set this bit to isolate isa bus. 5 en_clkout_pd r/w vdd3v enable clkout1 and clkout2 power down when isolate the isa bus. 4 en_sysclk_pd r/w vdd3v enable sysclk to power down when isolate the isa bus. 3 en_refresh r/w vdd3v enable refresh output. 2 dis_clkout2 r/w vdd3v if this bit set to 1, clkout2 will power down. 1 dis_clkout1 r/w vdd3v if this bit set to 1, clkout1 will power down. 0 en_gpio r/w vdd3v set this bit to enab le write command to reg 0x11~0x1a. 8.7 gpio port define register (low byte)? index 11h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 gp_addr[7:0] r/w vdd3v user defines port address to control gp io functions. to control gpio state without entry configure mode. (if gpio no enable ?cr10 bit0?, this register will read only). for example: if define gp_addr 0x150 in cr11 and cr12t. if(gpio output ctrl (reg 0x15, 0x18) set to output mode then: -o 150 aa (10101010b) to set gp17, gp15, gp13 and gp11 to high. -o 150 55 (01010101 b) to set gp16, gp14, gp12 and gp10 to high. -o 151 aa (10101010b) to set gp23 and gp21 to high. -o 151 55 (01010101 b) to set gp22 and gp20 to high. if(gpio output ctrl (reg 0x15, 0x18) set to input mode then: - i 150 ------show pin states of gp1[7..0]. - i 151------show pin states of gp2[3..0].
finte k feature integration technology inc. f85226 july, 2007 v0.25p 19 f8522 6 8.8 gpio port define regist er (high byte)? index 12h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 gp_addr[15:8] r/w vdd3v user defines port address to control gpio functions. to control gpio state without entry configure mode. (if gpio no enable ?cr10 bit0?, this register will read only). for example: if define gp_addr 0x150 in cr11 and cr12t. if(gpio output ctrl (reg 0x15, 0x18) set to output mode then: -o 150 aa (10101010b) to set gp17, gp15, gp13 and gp11 to high. -o 150 55 (01010101 b) to set gp16, gp14, gp12 and gp10 to high. -o 151 aa (10101010b) to set gp23 and gp21 to high. -o 151 55 (01010101 b) to set gp22 and gp20 to high. if(gpio output ctrl (reg 0x15, 0x18) set to input mode then: -i 150 ------ show pin states of gp1[7..0]. -i 151 ------ show pin states of gp2[3..0]. 8.9 address decoder regi ster (i) ? index 013h power-on default [7:0] =1111_1111b bit name r/w pwr description 7-4 decoder_sel2 r/w vdd3v select gpio pin to be gpcs2# that define decode address by cr21, 22. (if gpio no enable ?cr10 bit0?, this register will read only). 0000: if decode_sel2 set to 0x0h t he gpcs2 will output from pin gp10. 0011: if decode_sel2 set to 0x3h t he gpcs2 will output from pin gp13. 0100: if decode_sel2 set to 0x4h t he gpcs2 will output from pin gp14. 0101: if decode_sel2 set to 0x5h t he gpcs2 will output from pin gp15. 1000: if decode_sel2 set to 0x8h t he gpcs2 will output from pin gp20. 1001: if decode_sel2 set to 0x9h t he gpcs2 will output from pin gp21. 1010: if decode_sel2 set to 0xah the gpcs2 will output from pin gp22. 1011: if decode_sel2 set to 0xbh the gpcs2 will output from pin gp23. default : disable. 3-0 decoder_sel1 r/w vdd3v select gpio pin to be gpcs2# that define decode address by cr24, 25. (if gpio no enable ?cr10 bit0?, this register will read only). 0000: if decode_sel1 set to 0x0h t he gpcs1 will output from pin gp10. 0011: if decode_sel1 set to 0x3h t he gpcs1 will output from pin gp13. 0100: if decode_sel1 set to 0x4h t he gpcs1 will output from pin gp14. 0101: if decode_sel1 set to 0x5h t he gpcs1 will output from pin gp15. 1000: if decode_sel1 set to 0x8h t he gpcs1 will output from pin gp20.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 20 f8522 6 1001: if decode_sel1 set to 0x9h t he gpcs1 will output from pin gp21. 1010: if decode_sel1 set to 0xah the gpcs1 will output from pin gp22. 1011: if decode_sel1 set to 0xbh the gpcs1 will output from pin gp23. default: disable. 8.10 address decoder regist er (ii) ? index 014h power-on default [7:0] =1111_1111b bit name r/w pwr description 7-4 decoder_sel4 r/w vdd3v select gpio pin to be gpcs3# that define decode address by cr31, 32. (if gpio no enable ?cr10 bit0?, this register will read only). 0000: if decode_sel4 set to 0x0h t he gpcs4 will output from pin gp10. 0011: if decode_sel4 set to 0x3h t he gpcs4 will output from pin gp13. 0100: if decode_sel4 set to 0x4h t he gpcs4 will output from pin gp14. 0101: if decode_sel4 set to 0x5h t he gpcs4 will output from pin gp15. 1000: if decode_sel4 set to 0x8h t he gpcs4 will output from pin gp20. 1001: if decode_sel4 set to 0x9h t he gpcs4 will output from pin gp21. 1010: if decode_sel4 set to 0xah the gpcs4 will output from pin gp22. 1011: if decode_sel4 set to 0xbh the gpcs4 will output from pin gp23. default: disable. 3-0 decoder_sel3 r/w vdd3v select gpio pin to be gpcs3# that define decode address by cr34, 35. (if gpio no enable ?cr10 bit0?, this register will read only). 0000: if decode_sel3 set to 0x0h t he gpcs3 will output from pin gp10. 0011: if decode_sel3 set to 0x3h t he gpcs3 will output from pin gp13. 0100: if decode_sel3 set to 0x4h t he gpcs3 will output from pin gp14. 0101: if decode_sel3 set to 0x5h t he gpcs3 will output from pin gp15. 1000: if decode_sel3 set to 0x8h t he gpcs3 will output from pin gp20. 1001: if decode_sel3 set to 0x9h t he gpcs3 will output from pin gp21. 1010: if decode_sel3 set to 0xah the gpcs3 will output from pin gp22. 1011: if decode_sel3 set to 0xbh the gpcs3 will output from pin gp23. default: disable. 8.11 gpio input control register ? index 15h power-on default [7:0] =0000_0000b bit name r/w pwr description 7 gp17_octrl r/w vdd3v gp17 in/out mode select: gp17 is input mode if set to 0. gp17 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 6 gp16_octrl r/w vdd3v gp16 in/out mode select: gp16 is input mode if set to 0. gp16 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 5 gp15_octrl r/w vdd3v gp15 in/out mode select: gp15 is input mode if set to 0. gp15 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only).
finte k feature integration technology inc. f85226 july, 2007 v0.25p 21 f8522 6 4 gp14_octrl r/w vdd3v gp14 in/out mode select: gp14 is input mode if set to 0. gp14 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 3 gp13_octrl r/w vdd3v gp13 in/out mode select: gp13 is input mode if set to 0. gp13 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 2 gp12_octrl r/w vdd3v gp12 in/out mode select: gp12 is input mode if set to 0. gp12 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 1 gp11_octrl r/w vdd3v gp11 in/out mode select: gp11 is input mode if set to 0. gp11 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 0 gp10_octrl r/w vdd3v gp10 in/out mode select: gp10 is input mode if set to 0. gp10 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 8.12 gpio output data register ? index 16h power-on default [7:0] =0000_0000b bit name r/w pwr description 7 gp17_data r/w vdd3v when gp17 in out mode, set this bit to write data to pin gp17. (if gpio no enable ?cr10 bit0?, this register will read only). 6 gp16_data r/w vdd3v when gp16 in out mode, set this bit to write data to pin gp16. (if gpio no enable ?cr10 bit0?, this register will read only). 5 gp15_data r/w vdd3v when gp15 in out mode, set this bit to write data to pin gp15. (if gpio no enable ?cr10 bit0?, this register will read only). 4 gp14_data r/w vdd3v when gp14 in out mode, set this bit to write data to pin gp14. (if gpio no enable ?cr10 bit0?, this register will read only). 3 gp13_data r/w vdd3v when gp13 in out mode, set this bit to write data to pin gp13. (if gpio no enable ?cr10 bit0?, this register will read only). 2 gp12_data r/w vdd3v when gp12 in out mode, set this bit to write data to pin gp12. (if gpio no enable ?cr10 bit0?, this register will read only). 1 gp11_data r/w vdd3v when gp11 in out mode, set this bit to write data to pin gp11. (if gpio no enable ?cr10 bit0?, this register will read only). 0 gp10_data r/w vdd3v when gp10 in out mode, set this bit to write data to pin gp10. (if gpio no enable ?cr10 bit0?, this register will read only). 8.13 gpio1x input register ? index 17h power-on default [7:0] =pppp_ppppb (p: mean pin status) bit name r/w pwr description 7 gp17_st ro vdd3v this bit is read only, when read back is the status of the pin gp17.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 22 f8522 6 6 gp16_st ro vdd3v this bit is read only, when read back is the status of the pin gp16. 5 gp15_st ro vdd3v this bit is read only, when read back is the status of the pin gp15. 4 gp14_st ro vdd3v this bit is read only, when read back is the status of the pin gp14. 3 gp13_st ro vdd3v this bit is read only, when read back is the status of the pin gp13. 2 gp12_st ro vdd3v this bit is read only, when read back is the status of the pin gp12. 1 gp11_st ro vdd3v this bit is read only, wh en read back is the status of the pin gp11. 0 gp10_st ro vdd3v this bit is read only, when read back is the status of the pin gp10. 8.14 gpio2 input control register ? index 18h power-on default [7:0] =0000_0000b bit name r/w pwr description 7 reserved - - reserved. 3 gp23_octrl r/w vdd3v gp23 in/out mode select: gp23 is input mode if set to 0. gp23 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 2 gp22_octrl r/w vdd3v gp22 in/out mode select: gp22 is input mode if set to 0. gp22 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 1 gp21_octrl r/w vdd3v gp21 in/out mode select: gp21 is input mode if set to 0. gp21 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 0 gp20_octrl r/w vdd3v gp20 in/out mode select: gp20 is input mode if set to 0. gp20 is output mode if set to 1. (if gpio no enable ?cr10 bit0?, this register will read only). 8.15 gpio2 output data register ? index 19h power-on default [7:0] =0000_0000b bit name r/w pwr description 7 reserved r/w vdd3v reserved 3 gp23_data r/w vdd3v when gp23 in out mode, set this bit to write data to pin gp23. (if gpio no enable ?cr10 bit0?, this register will read only). 2 gp22_data r/w vdd3v when gp22 in out mode, set this bit to write data to pin gp22. (if gpio no enable ?cr10 bit0?, this register will read only). 1 gp21_data r/w vdd3v when gp21 in out mode, set this bit to write data to pin gp21. (if gpio no enable ?cr10 bit0?, this register will read only). 0 gp20_data r/w vdd3v when gp20 in out mode, set this bit to write data to pin gp20. (if gpio no enable ?cr10 bit0?, this register will read only).
finte k feature integration technology inc. f85226 july, 2007 v0.25p 23 f8522 6 8.16 gpio2 input register ? index 1ah power-on default [7:0] =0000_ppppb (p: mean pin status) bit name r/w pwr description 7-4 reserved r/w vdd3v reserved 3 gp23_ st r/w vdd3v this bit is read only, wh en read back is the status of the pin gp23. 2 gp22_ st r/w vdd3v this bit is read only, wh en read back is the status of the pin gp22. 1 gp21_ st r/w vdd3v this bit is read only, wh en read back is the status of the pin gp21. 0 gp20_ st r/w vdd3v this bit is read only, wh en read back is the status of the pin gp20. 8.17 led & irqin control register ? index 1bh power-on default [7:0] =0000_0000b bit name r/w pwr description 7 addr_dec_ty pe[1] r/w vdd3v if set to 1, the address decode 4 (cr34, cr35) will decode the memory cycle, else it will decode io cycle. 6 addr_dec_ty pe[0] r/w vdd3v if set to 1, the address decode 3 (cr31, cr32) will decode the memory cycle, else it will decode io cycle. 5-4 led_freq r/w vdd3v when pin gp14 or gp20 be selected to led mode, user can use these two bits to define led frequency: 00: power led pin is tri-stated. 01: power led pin is driven low. 10: power led pin is a 1hz toggle pulse with 50 duty cycle. 11: power led pin is a 1/2 hz toggle pulse with 50 duty cycle. 3-0 irqin_sel r/w vdd3v these bits select irq resource for irqin. four bits transfer the decimal value to octal system. for example: bit [3..0] = 1001b = 0x9h means irq 9 be selected. bit [3..0] = 1100b = 0xch means irq12 be selected. 8.18 master setting re gister ? index 1ch power-on default [7:0] =1110_0001b bit name r/w pwr description 7-0 en_master16_ch r/w vdd3v reserved
finte k feature integration technology inc. f85226 july, 2007 v0.25p 24 f8522 6 8.19 master setting re gister ? index 1dh power-on default [7:0] =0110_0011b bit name r/w pwr description 7 en_timeout r/w vdd3v enable this bit to timeout lpc long wait when isa bus had pull iochrdy to low. 6-0 timeout_value r/w vdd3v define the timeout value, the unit is isa system clock. so if isa pull iochrdy to low more then this time, the device will end of the lpc long wait. (default are 100 isa clock) 8.20 refresh address register (low byte) ? index 1eh power-on default [7:0] =1111_1111b bit name r/w pwr description 7-0 refresh_addr r/w vdd3v cr 1e, 1f are used to define the refresh co unter repeat value: for example, if set refresh_addr to 0x01ff, the address in refresh will increase until reach 0x01ff and then refresh address return to 0x0000. 8.21 refresh address register (high byte) ? index 1fh power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 refresh_addr r/w vdd3v cr 1e, 1f are used to define the refresh co unter repeat value: for example, if set refresh_addr to 0x01ff, the address in refresh will increase until reach 0x01ff and then refresh address return to 0x0000. 8.22 address1 decode mask register ? index 20h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr_mask1 r/w vdd3v this register is used to mask address bits (a7~a0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignored by the specify address decoder. for example: if the decoding range is 0x3f8 ~ 0x3ff, you can set 0x03f8 to cr21, 22 and 07h to cr20. 8.23 address1 decode register (low byte) ? index 21h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr_dec1 r/w vdd3v this register contains the address for specify decoder.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 25 f8522 6 cr21 bit [7..0] are used to define low byte of specify address. cr22 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x3f5h when wrote f5h to cr21 and 03h to cr22. 8.24 address1 decode register (high byte) ? index 22h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr_dec1 r/w vdd3v this register contains the address for specify decoder. cr21 bit [7..0] are used to define low byte of specify address. cr22 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x3f5h when wrote f5h to cr21 and 03h to cr22. 8.25 address2 decode mask register ? index 23h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr_mask2 r/w vdd3v this register is used to mask address bits (a7~a0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignored by the specify address decoder. for example: if the decoding range is 0x3f8 ~ 0x3ff, you can set 0x03f8 to cr24, 25 and 07h to cr23. 8.26 address2 decode register (low byte) ? index 24h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr_dec2 r/w vdd3v this register contains the address for specify decoder. cr24 bit [7:0] are used to define low byte of specify address. cr25 bit [7:0] are used to define high byte of specify address. for example: decoding address was set to be 0x3f5h when wrote f5h to cr24 and 03h to cr25. 8.27 address2 decode register (high byte) ? index 25h power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr_dec2 r/w vdd3v this register contains the address for specify decoder. cr24 bit [7..0] are used to define low byte of specify address. cr25 bit [7..0] are used to define high byte of specify address.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 26 f8522 6 for example: decoding address was set to be 0x3f5h when wrote f5h to cr24 and 03h to cr25 . 8.28 rom1 decoder mask low byte register ? index 0x28 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_mask1 r/w vdd3v the register cr28, 29 are used to mask addr ess bits (a19~a4) for specify address decoder, if the corresponding bit of this r egister is set to a 1, the corresponding address bit(a19~a4) is ignored by the specify address decoder. for example: if the decoding range is 0xf_fffx ~ 0xf_e00x, you can set 0xf_ffff to cr2a, 2b and ffh to cr28, 01h to cr29. 8.29 rom decoder mask (high byte) register ? index 0x29 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_ mask1 r/w vdd3v the register cr28, 29 are used to mask addr ess bits (a19~a4) for specify address decoder, if the corresponding bit of this r egister is set to a 1, the corresponding address bit(a19~a4) is ignored by the specify address decoder. for example: if the decoding range is 0xf_fffx ~ 0xf_e00x, you can set 0xf_ffff to cr2a, 2b and ffh to cr28, 01h to cr29. 8.30 rom decoder address (low byte) register ? index 0x2a power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_dec1 r/w vdd3v this register contains the address for specify decoder. cr2a bit [7..0] are used to define low address[11:4]. cr2b bit [7..0] are used to define high address[19:12]. for example: decoding address was set to be 0xf_feexh when wrote eeh to cr2a and ffh to cr2b. 8.31 rom decoder address (high byte) register ? index 0x2b power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_dec1 r/w vdd3v this register contains the address for specify decoder. cr2a bit [7..0] are used to define low address[11:4]. cr2b bit [7..0] are used to define high address[19:12]. for example: decoding address was set to be 0xf_feexh when wrote eeh to cr2a and ffh to cr2b.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 27 f8522 6 8.32 rom2 decoder mask low byte register ? index 0x2c power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_mask2 r/w vdd3v the register cr2c, 2d are used to mask ad dress bits (a19~a4) for specify address decoder, if the corresponding bit of this r egister is set to a 1, the corresponding address bit(a19~a4) is ignored by the specify address decoder. for example: if the decoding range is 0xf_fffx ~ 0xf_e00x, you can set 0xf_ffff to cr2e, 2f and ffh to cr2c, 01h to cr2d. 8.33 rom2 decoder mask (high byte) register ? index 0x2d power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_ mask2 r/w vdd3v the register cr2c, 2d are used to mask ad dress bits (a19~a4) for specify address decoder, if the corresponding bit of this r egister is set to a 1, the corresponding address bit(a19~a4) is ignored by the specify address decoder. for example: if the decoding range is 0xf_fffx ~ 0xf_e00x, you can set 0xf_ffff to cr2e, 2f and ffh to cr2c, 01h to cr2d. 8.34 rom2 decoder address (low byte) register ? index 0x2e power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_dec2 r/w vdd3v this register contains the address for specify decoder. cr2e bit [7..0] are used to define low address[11:4]. cr2f bit [7..0] are used to define high address[19:12]. for example: decoding address was set to be 0x5_5aaxh when wrote aah to cr2e and 55h to cr2f. 8.35 rom2 decoder address (high byte) register ? index 0x2f power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rom_dec2 r/w vdd3v this register contains the address for specify decoder. cr2e bit [7..0] are used to define low address[11:4]. cr2f bit [7..0] are used to define high address[19:12]. for example: decoding address was set to be 0x5_5aaxh when wrote aah to cr2e and 55h to cr2f.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 28 f8522 6 8.36 addr3 decoder mask high byte register ? index 0x30 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr3_dec_mask r/w vdd3v this register is used to mask io address bits a7~a0 or memory addrss bits a23~a16 for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bits will ignored by the specify address decoder. for example: if the decoding range is 0x3f8 ~ 0x3ff, you can set 0x03f8 to cr31, 32 and 07h to cr30. 8.37 addr3 decoder address low byte register ? index 0x31 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr3_dec r/w vdd3v this register contains the address for specify decoder. cr31 bit [7..0] are used to define low byte of specify address. cr32 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x3f5h when wrote f5h to cr31 and 03h to cr32. (the address decoder will decode the match ?io? address that define in cr31 and cr32 register, but when set cr1b bit6 to 1, the address decoder will decode the match ?memory? address[31:16] that define in cr31 and cr32 registers). 8.38 addr3 decoder address high byte register ? index 0x32 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr3_dec r/w vdd3v this register contains the address for specify decoder. cr31 bit [7..0] are used to define low byte of specify address. cr32 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x3f5h when wrote f5h to cr31 and 03h to cr32. (the address decoder will decode the match ?io? address that define in cr31 and cr32 register, but when set cr1b bit6 to 1, the address decoder will decode the match ?memory? address[31:16] that define in cr31 and cr32 registers). 8.39 addr4 decoder mask high byte register ? index 0x33 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr4_dec_mask r/w vdd3v this register is used to mask io address bits a7~a0 or memory addrss bits
finte k feature integration technology inc. f85226 july, 2007 v0.25p 29 f8522 6 a23~a16 for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bits will ignored by the specify address decoder. for example: if the decoding range is 0x3f8 ~ 0x3ff, you can set 0x03f8 to cr34, 35 and 07h to cr33. 8.40 addr4 decoder address low byte register ? index 0x34 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr4_dec r/w vdd3v this register contains the address for specify decoder. cr34 bit [7..0] are used to define low byte of specify address. cr35 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x3f5h when wrote f5h to cr34 and 03h to cr35. (the address decoder will decode the match ?io? address that define in cr34 and cr35 register, but when set cr1b bit7 to 1, the address decoder will decode the match ?memory? address[31:16] that define in cr34 and cr35 registers). 8.41 addr4 decoder address high byte register ? index 0x35 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 addr4_dec r/w vdd3v this register contains the address for specify decoder. cr34 bit [7..0] are used to define low byte of specify address. cr35 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x3f5h when wrote f5h to cr34 and 03h to cr35. (the address decoder will decode the match ?io? address that define in cr34 and cr35 register, but when set cr1b bit7 to 1, the address decoder will decode the match ?memory? address[31:16] that define in cr34 and cr35 registers). 8.42 kbc decoder mask register ? index 0x36 power-on default [7:0] =0000_0100b bit name r/w pwr description 7-0 kbc _mask r/w vdd3v this register is used to mask address bits (a7~a0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignored by the specify address decoder. for example: if the decoding range is 0x060 & 0x064, you can set 0x060 to cr37, 38 and 04h to cr36.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 30 f8522 6 8.43 kbc decoder address low byte register ? index 0x37 power-on default [7:0] =0110_0000b bit name r/w pwr description 7-0 kbc_dec r/w vdd3v this register contains the address for kbc decoder. cr37 bit [7..0] are used to define low byte of specify address. cr38 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x060h when wrote 60h to cr37 and 00h to cr38. 8.44 kbc decoder address high by te register ? index 0x38 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 kbc_dec r/w vdd3v this register contains the address for kbc decoder. cr37 bit [7..0] are used to define low byte of specify address. cr38 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x060h when wrote 60h to cr37 and 00h to cr38. 8.45 mc decoder mask register ? index 0x39 power-on default [7:0] =0000_0100b bit name r/w pwr description 7-0 mc _mask r/w vdd3v this register is used to mask address bits (a7~a0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignored by the specify address decoder. for example: if the decoding range is 0x062 & 0x066, you can set 0x062 to cr3a, 3b and 04h to cr39. 8.46 mc decoder address low byte register ? index 0x3a power-on default [7:0] =0110_0010b bit name r/w pwr description 7-0 mc_dec r/w vdd3v this register contains the address for kbc decoder. cr3a bit [7..0] are used to define low byte of specify address. cr3b bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x062h when wrote 60h to cr3a and 00h to cr3b.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 31 f8522 6 8.47 mc decoder address high byte register ? index 0x3b power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 mc_dec r/w vdd3v this register contains the address for kbc decoder. cr3a bit [7..0] are used to define low byte of specify address. cr3b bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x062h when wrote 60h to cr3a and 00h to cr3b. 8.48 rtc decoder mask register ? index 0x3c power-on default [7:0] =0000_0001b bit name r/w pwr description 7-0 rtc_ mask r/w vdd3v this register is used to mask address bits (a7~a0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignored by the specify address decoder. for example: if the decoding range is 0x07 0 & 0x071, you can set 0x070 to cr3d, 3e and 01h to cr3c. 8.49 rtc decoder address low by te register ? index 0x3d power-on default [7:0] =0111_0000b bit name r/w pwr description 7-0 rtc_dec r/w vdd3v this register contains the address for kbc decoder. cr3d bit [7..0] are used to define low byte of specify address. cr3e bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x060h when wrote 70h to cr3d and 00h to cr3e. 8.50 rtc decoder address high byte register ? index 0x3e power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 rtc_dec r/w vdd3v this register contains the address for kbc decoder. cr3d bit [7..0] are used to define low byte of specify address. cr3e bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x060h when wrote 70h to cr3d and 00h to cr3e.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 32 f8522 6 8.51 ioh decoder mask register ? index 0x3f power-on default [7:0] =1111_1111b bit name r/w pwr description 7-0 ioh_ mask r/w vdd3v this register is used to mask address bits (a7~a0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignored by the specify address decoder. for example: if the decoding range is 0x0000 ~ 0x00ff, you can set 0x00 to cr40, 41 and ffh to cr3f. 8.52 ioh decoder address low byte register ? index 0x40 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 ioh_dec r/w vdd3v this register contains the address for kbc decoder. cr40 bit [7..0] are used to define low byte of specify address. cr41 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x0080h when wrote 80h to cr40 and 00h to cr41. 8.53 ioh decoder address high byte register ? index 0x41 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-0 ioh_dec r/w vdd3v this register contains the address for kbc decoder. cr40 bit [7..0] are used to define low byte of specify address. cr41 bit [7..0] are used to define high byte of specify address. for example: decoding address was set to be 0x0080h when wrote 80h to cr40 and 00h to cr41. 8.54 edge detector stat us register ? index 0x50 power-on default [7:0] =0000_0000b bit name r/w pwr description 7-1 reserved ro vdd3v reserved 0 clk_pd rw vdd3v set to 1 to disable sysclk output.
finte k feature integration technology inc. f85226 july, 2007 v0.25p 33 f8522 6 8.55 irq wakeup register (i) ? index 0x51 power-on default [7:0] =0000_0000b bit name r/w pwr description 7 en_irq7_w rw vdd3v set to 1 to enable irq7 to wakeup the system. 6 en_irq6_w r/w vdd3v set to 1 to enable irq6 to wakeup the system. 5 en_irq5_w r/w vdd3v set to 1 to enable irq5 to wakeup the system. 4 en_irq4_w r/w vdd3v set to 1 to enable irq4 to wakeup the system. 3 en_irq3_w r/w vdd3v set to 1 to enable irq3 to wakeup the system. 2 reserved r/w vdd3v reserved 1 en_irq1_w r/w vdd3v set to 1 to enable irq1 to wakeup the system. 0 en_pwrdn_w rw vdd3v set to 1 to enable pwrdn pin to power down or wakeup the system. 8.56 irq wakeup register (ii) ? index 0x52 power-on default [7:0] =0000_0000b bit name r/w pwr description 7 reserved rw vdd3v reserved 6 en_irq15_w r/w vdd3v set to 1 to enable irq15 to wakeup the system. 5 en_irq14_w r/w vdd3v set to 1 to enable irq14 to wakeup the system. 4 en_irq12_w r/w vdd3v set to 1 to enable irq12 to wakeup the system. 3 en_irq11_w r/w vdd3v set to 1 to enable irq11 to wakeup the system. 2 en_irq10_w r/w vdd3v set to 1 to enable irq10 to wakeup the system. 1 en_irq9_w r/w vdd3v set to 1 to enable irq9 to wakeup the system. 0 en_irq8_w rw vdd3v set to 1 to enable irq8 to wakeup the system. 8.57 chipid (1) register ? index 5ah power-on default [7:0] =0000_0011b bit name r/w pwr description 7-0 chipid ro vdd3v chip id, high byte (8?h03). 8.58 chipid (2) register ? index 5bh power-on default [7:0] =0000_0101b bit name r/w pwr description 7-0 chipid ro vdd3v chip id, low byte (8?h05).
finte k feature integration technology inc. f85226 july, 2007 v0.25p 34 f8522 6 8.59 version register ? index 5ch power-on default [7:0] =0001_0000b bit name r/w pwr description 7-0 version ro vdd3v version 1.0. 8.60 vendor id (1) register ? index 5dh power-on default [7:0] =0001_1001b bit name r/w pwr description 7-0 vendor1 ro vdd3v vendor id, 8?h19. 8.61 vendor id (2) register ? index 5eh power-on default [7:0] =0011_0100b bit name r/w pwr description 7-0 vendor2 ro vdd3v vendor id, 8h34. 9. ordering information part number package type production flow F85226F 128 pin pqfp (normal) commercial, 0 c to +70 c F85226Fg 128 pin pqfp (green package) commercial, 0 c to +70 c 10. electrical characteristic 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device
finte k feature integration technology inc. f85226 july, 2007 v0.25p 35 f8522 6 9.2 dc characteristics (ta = 70 c, vdd = 3.3v, vss = 0v) parameter sym. min. typ. max. unit conditions i/od 24ts - ttl level bi-directional pin, with schmitt tri gger, can select to od by register, with 24 ma source-sink capability input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v output low current iol 24 ma vol = 0.4 v input high leakage ilih 1 a vin = vdd input low leakage ilil -1 a vin = 0v i/o24 ts - ttl level bi-directional pin, with schmi tt trigger and 24 ma source-sink capability input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v output high current ioh -24 ma vol = 2.4 v output low current iol 24 ma vol = 0.4 v input high leakage ilih 1 a vin = vdd input low leakage ilil -1 a vin = 0v o 20 - output pin with 20 ma source-sink capability output high current ioh -20 ma vol = 2.4 v output low current iol 20 ma vol = 0.4 v o 24 - output pin with 24 ma source-sink capability output high current ioh -24 ma vol = 2.4 v output low current iol 24 ma vol = 0.4 v in t - ttl level input pin input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v input high leakage ilih 1 a vin = vdd input low leakage ilil -1 a vin = 0v in ts - ttl level input pin with schmitt trigger input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v input high leakage ilih 1 a vin = vdd input low leakage ilil -1 a vin = 0v
finte k feature integration technology inc. f85226 july, 2007 v0.25p 36 f8522 6 11. package specification 128 pqfp feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r
finte k feature integration technology inc. f85226 july, 2007 v0.25p 37 f8522 6 12. application circuit rtc_en select rtc_en dack1# pwr_pd memr # memr# sa3 master# sa18 r4 on rtc_en on r4 off rtc_en off rom_en select irq6 r2 10k sa0 vcc3v iochrdy sa5 rtc en dack0# vcc3v drq3 lfram# r3 on access port = 2eh r3 off access port = 4eh iow# drq2 4e_en sd5 rtccs# sa12 sa[18..0] drq1 r1 4.7k bale sd8 sd[7..0] memw # sa11 sd14 gp15 sd15 u2 1 30 2 3 29 28 4 25 23 26 27 5 6 7 8 13 14 15 17 18 19 20 21 32 16 9 10 11 22 24 31 12 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 vcc gnd a3 a2 a1 ce# oe# we# a0 sy sclk irq11 sa15 irq15 irq12 drq0 r1 on rom_en on r1 off rom_en off irq9 pciclk lad0 dack6# sd6 irq14 sa6 r3 10k la21 u1 F85226F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 drq5 dack5# drq0 dack0# vcc1 irq14 irq15 irq12 irq11 irq10 iocs16# memcs16# lfram# lreset# gnd lad3 lad2 lad1 lad0 vcc2 pciclk ldrq# serirq lpc_pd# vcc3 clkin clkout1 clkout2 gp23 gnd sa0 sa1 sa2 sa3 sa4 80cs#/kben# romcs# gpio0/irq1 gpio1/kbcs# gpio2/mscs# sa5 sa6 sa7 sa8 vcc4 sa9 sa10 sa11 sa12 gnd sa13 sa14 sa15 sa16 vcc sa17 sa18 sa19 aen gnd iochrdy gpio3/irqin gpio4/pled gpio5/irq8 gpio6/rtccs# gpio7/iocs# sd0 sd1 sd2 vcc5 sd3 sd4 sd5 sd6 sd7 iochk# rstdrv irq9 drq2 gnd ows# smemw# smemr# iow# vcc6 ior# dack3# drq3 dack1# drq1 refresh# sysclk irq7 irq6 gnd irq5 irq4 irq3 dack2# tc bale sbhe# la23 la22 vcc7 la21 la20 la19 la18 gnd la17 memr # memw # sd8 sd9 sd10 sd11 sd12 sd13 vcc8 sd14 sd15 master# drq7 gnd dack7# drq6 dack6# 14.318m kb en sa1 vcc3v la23 sa19 irq10 sa13 gp16 ows# serirq la20 c3 0.1u sbhe# sd0 sa9 drq6 la22 dack5# sd10 vcc3v r5 10k ior# clkout2 dack3# gp14 r2 on kb_en on r2 off kb_en off c1 0.1u kb_en c4 0.1u ldrq# c2 0.1u sd4 sa17 smemw# memc s16# aen la17 lad1 rstdrv sa2 lad3 sd3 dack2# sd2 irq8 sa4 F85226F application circuit b 13 monday , august 16, 2004 tit le size document number rev date: sheet of la19 irq5 gp23 iochck# vcc3v r4 10k gp11 kb_en select 4e en clkout1 sd1 sa10 refresh# kbcs# sa7 rom_en drq7 dack7# pcirst# tc la18 sa14 vcc3v gp13 sd11 4e_en select gp12 irq1 sd13 memw # gp17 sa16 sd9 smemr# mccs# rom en lad[3..0] irq7 lad2 irq4 sd7 sa8 sd12 iocs16# drq5 irq3 f85226
finte k feature integration technology inc. f85226 july, 2007 v0.25p 38 f8522 6 r70 r r35 r r34 8.2k r44 r r48 1k irq14 r57 r la19 r43 r r47 r +12v r64 r c19 10u r81 r irq6 sd10 ows# c13 0.1u c21 10u r84 r master # vcc5v r59 r r28 1k c9 0.1u r45 1k j6 con2 1 2 drq6 c20 10u sd6 c11 0.1u c22 10u sa18 r36 8.2k sa15 vcc5v r49 8.2k drq2 r24 r r76 r j5 con2 1 2 r65 r sa2 sa3 sa19 drq7 r93 r r50 r r69 r r31 8.2k la20 sd4 irq12 iow# r66 r j4 con2 1 2 r85 r ior# r26 r r37 r irq9 sa9 sd9 r60 r sa5 sa4 sd13 r52 r la18 r71 r r77 r sd0 iochrdy vcc5v sa12 irq7 r61 r r86 r r27 r r39 1k sa1 sa0 vcc3v sa14 sd1 irq5 memc s16# -5v memw # r72 r c15 0.1u drq1 sd12 r42 1k r51 8.2k r29 r r53 r sa13 irq15 smemw# r38 r sa17 la17 drq5 r73 r r87 r c17 0.1u sd2 r78 r r40 r irq10 smemr# iochck# r30 r r79 r r54 r c18 0.1u r88 r irq3 c8 10u c10 10u la22 sa11 la23 sd7 r62 r r20 r vcc5v r74 r r22 4.7k c16 0.1u r67 r r91 r r55 r drq0 memr # vcc3v drq3 c14 0.1u r41 r -12v r21 r irq4 sd11 r63 r r89 r sa8 sd5 sa16 irq11 sa7 iocs16# r58 r r68 r r46 r refresh# r32 r sa6 r56 r sd15 F85226F application circuit b 23 tuesday , december 23, 2003 tit le size document number rev date: sheet of r80 r sd14 r33 1k r23 r c12 10u r83 r sd3 r75 r r82 r r90 r r92 r la21 sa10 sd8 r25 1k
finte k feature integration technology inc. f85226 july, 2007 v0.25p 39 f8522 6 drq0 sa0 sbhe# sd14 sa4 irq5 sd9 sa11 sa7 drq0 j7 a/b channel 1 32 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 iochck# gnd resdrv sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 iordy aen sa19 sa18 sa17 sa16 sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 +5v irq9 -5v drq2 -12v 0ws +12v gnd smemw# smemr# iow# ior# dack3# drq3 dack1# drq1 ref# clk irq7 irq6 irq5 irq4 irq3 dack2# t/ c bale +5 osc gnd sd1 la21 memr # sd3 sa5 sd9 sd15 dack0# sa3 sa14 sd0 c26 0.1u sa12 drq7 sd11 sd15 bale -5v irq15 sa13 irq15 irq7 iocs16# dack1# +12v sa2 sa13 irq9 dack2# mecs16# sa18 osc dack3# -12v c27 0.1u iocs16# sd13 dack6# drq3 sd6 c28 0.1u sa8 sd9 smemr# dack5# sa19 sa12 sa11 sd5 iochrdy la18 master# sd10 drq0 memr # sd2 master# sysclk la19 irq15 j11 c/d channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 sbhe la23 la22 la21 la20 la19 la18 la17 memr # memw # sd08 sd09 sd10 sd11 sd12 sd13 sd14 sd15 gnd master # +5v drq7 dack7# drq6 dack6# drq5 dack5# drq0 dack0# irq14 irq15 irq12 irq11 irq10 iocs16# mecs16# sd5 irq7 sd15 c23 0.1u irq14 la22 la23 irq3 irq10 sd6 tc sd0 irq9 irq11 irq11 sd11 mecs16# drq1 iow# aen sa16 smemr# sa10 c25 0.1u sd11 dack3# la18 iocs16# smemr# sa13 sa6 j12 c/d channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 sbhe la23 la22 la21 la20 la19 la18 la17 memr # memw # sd08 sd09 sd10 sd11 sd12 sd13 sd14 sd15 gnd master# +5v drq7 dack7# drq6 dack6# drq5 dack5# drq0 dack0# irq14 irq15 irq12 irq11 irq10 iocs16# mec s16# sd6 j8 a/b channel 1 32 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 iochck# gnd resdrv sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 iordy aen sa19 sa18 sa17 sa16 sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 +5v irq9 -5v drq2 -12v 0ws +12v gnd smemw# smemr# iow# ior# dack3# drq3 dack1# drq1 ref# clk irq7 irq6 irq5 irq4 irq3 dack2# t/ c bale +5 osc gnd irq4 sd7 drq2 iochck# smemw# la18 master# drq6 irq6 tc dack3# tc sd8 ior# vcc5v memw # +12v sa1 sd14 -5v irq3 la19 sd5 irq3 la22 irq10 irq11 iochrdy irq12 c24 0.1u irq9 sa0 rstdrv la20 sa17 -12v la19 irq12 sa9 la23 ows# sa4 mec s16# la17 sa10 sa15 F85226F application circuit b 33 tuesday , december 23, 2003 tit le size document number rev date: sheet of sbhe# bale sd7 la23 j10 c/d channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 sbhe la23 la22 la21 la20 la19 la18 la17 memr # memw # sd08 sd09 sd10 sd11 sd12 sd13 sd14 sd15 gnd master# +5v drq7 dack7# drq6 dack6# drq5 dack5# drq0 dack0# irq14 irq15 irq12 irq11 irq10 iocs16# mecs16# iochck# sd12 irq10 drq2 sa7 smemw# sd8 drq6 sa6 dack7# drq1 sa6 memw # irq14 osc vcc5v sd4 sa8 sa18 iochrdy la22 sa10 drq2 rstdrv sa2 sd1 sa16 ows# drq6 irq6 drq5 sa17 drq7 irq5 sa4 ior# sa1 drq3 sa14 vcc5v iochck# sa15 sa9 iow# la21 sd2 dack0# irq4 sa3 dack5# la20 memr # sy sclk sd7 sa7 -5v memw # sd12 sd14 la17 ows# sa2 sa0 +12v sa5 dack1# sd3 dack2# irq14 la21 sbhe# rstdrv dack1# sd4 sd2 -12v sa18 drq5 ior# sa3 sd13 dack7# bale sd10 aen irq5 sa17 sa14 sa9 drq1 sa8 irq4 osc sa11 iow# sd3 irq12 sy sclk dack5# drq7 la20 sa15 sa5 dack0# sd13 sd12 la17 sa1 sa16 smemw# j9 a/b channel 1 32 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 iochck# gnd resdrv sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 iordy aen sa19 sa18 sa17 sa16 sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 +5v irq9 -5v drq2 -12v 0ws +12v gnd smemw# smemr# iow# ior# dack3# drq3 dack1# drq1 ref# clk irq7 irq6 irq5 irq4 irq3 dack2# t/ c bale +5 osc gnd sd8 drq3 dack7# sd1 sa19 dack2# sd10 drq5 sd0 irq7 sa12 irq6 aen dack6# sd4 dack6# sa19

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